VHDL Verification Opportunity

2 - 7 Years

Job Description

Job Description:

Mandatory : VHDL test-bench/component creation in verification

Experience in SOC/IP Verification
Hands on experience in creating test plan , development of test cases.
Must be expertise in System Verilog
Should have worked on OVM/UVM/VMM
Experience in debugging design with functional and code coverage closure.
Knowledge of protocols like Ethernet , PCIe , MIPI , USB will be a add-on.
Must have B.Tech/M.tech degree in Electrical and/or Electronics or equivalent

Salary: Not Disclosed by Recruiter


Desired Candidate Profile

Please refer to the Job description above

Company Profile

eInfochips Limited

Einfochips (An Arrow Company)

View Contact Details+

Recruiter Name:Einfochips Talent Acquisition

Contact Company:eInfochips Limited


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Functional Area

Engineering Design, R&D

Role Category

Engineering Design


Senior Design Engineer

Employment Type

Full Time, Permanent